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Architectural tricks to maximize memory bandwidth
This Webinar is over| Date | Feb 17, 2016 |
| Time | 02:00 PM EDT |
| Cost | Free |
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Online
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Unexplained Read/Write latency can be attributed to- cache hit-ratio, burst length, commands-in-a-row, AXI Bus arbitration, and video pipeline. During this Webinar, we will present the system-level modeling of complex video pipelines and their interface to memory using a Network of Buses. With this model, we shall optimize the address allocation to IP blocks, burst lengths and memory controller settings to get close to 98% efficiency.
We at Mirabilis Design have worked with a variety of architecture- processors, SoC, switches, multi-core and SSD controllers. We have cataloged our knowledge from these experiences to come up with a list of analysis, workload approaches and levels of abstractions. All of these are in a architecture exploration methodology that enables designers to gain extensive insight into the system operation.
Date : Wednesday, Feb 17, 2016
Time : 11 AM PST/ 2 PM EST
Duration : 1 Hour
Speakers : Deepak Shankar, CEO, Mirabilis Design Inc.
Case Studies : Darryl Koivisto, CTO, Mirabilis Design Inc.
We at Mirabilis Design have worked with a variety of architecture- processors, SoC, switches, multi-core and SSD controllers. We have cataloged our knowledge from these experiences to come up with a list of analysis, workload approaches and levels of abstractions. All of these are in a architecture exploration methodology that enables designers to gain extensive insight into the system operation.
Date : Wednesday, Feb 17, 2016
Time : 11 AM PST/ 2 PM EST
Duration : 1 Hour
Speakers : Deepak Shankar, CEO, Mirabilis Design Inc.
Case Studies : Darryl Koivisto, CTO, Mirabilis Design Inc.
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